WORKSHOP ON DESIGN WITH VERILOG

    WORKSHOP ON DESIGN WITH VERILOG

    Created by Electronics and Communication

    ASTHRA 8.0's "Design with Verilog" workshop is your gateway to digital circuit design. Learn the essentials of Verilog, explore key concepts like FSMs and data flow, and gain hands-on experience through projects and simulations. Master the skills to implement your designs on real-world platforms - register today! The participants will be awarded certificates that are eligible for KTU activity points.

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    WORKSHOP ON DESIGN WITH VERILOG

    Venue

    SJCET

    Event starts at

    4:30:00 AM

    Duration of event

    HALF DAY

    Amount

    ₹299

    FAQ: How is the registration works?

    Payment mode of event depends on category. Some events are free with ASTHRA PASS, but required to register.
    Sjcetians Don't need to buy ASTHRA PASS all Technical events are free for them, but WORKSHOP PASS should be purchased.
    Sjcetians are not allowed to compete in any competitions.
    Under any circumstances, If you buy any pass it won't be refunded.
    Before everything, you need to complete the profile. Make sure to complete the transaction without closing the page
    And finally you have to identify yourself once again to complete the transaction.